With regards to the features of the present invention, it is true that various kinds of integrated circuits are previously known where each input pad, output pad, and/or I/O-pad is equipped with, or coacts with, a test cell, thereby making it possible to test the complete integrated circuit.
Tests of this kind are performed either by applying required testing vectors to the input pads of the integrated circuit, or by applying necessary testing vectors through available test cells; for example, BS-cells.
The results of processing test vectors within the integrated circuit are observed at the output pads of the integrated circuit or through BS-output cells.
Regarding the illustrated embodiments in the description that follows, it can be mentioned that the circuit connections of the test cells may be of a standardized BS-structure.
Various circuit arrangements for the applications described above, and for the BS-cells that are connected to one other in order to form a Boundary-Scan-loop, hereafter called a BS-loop, are known and were previously shown through the publication IEEE Standard 1149.1 under the heading "IEEE Standard Test Access Port and Boundary-Scan Architecture".
Taking further notice of the feature of the present invention, and the primary application of a test cell or an output cell with an output pad, it can be mentioned, as an example of prior art, what was shown and described through the U.S. Pat. No. 5,319,646.
This publication is relevant since it describes a BS-output cell that is based on the basic circuit connection principally shown and described in FIG. 1 in the present application.
This circuit connection shows a BS-output cell with supplementary details such as a multiplexer 12; a selecting element 14; a shift register 16; and a hold element 18. The multiplexer 12 samples either critical data from a system logic that is separated from the BS-output cell through the control circuit 20, or test data from an earlier BS-output cell.
A first test-controlling circuit 19, in the form of an AND-gate, is connected to the selecting element 14.
With regards to supplementing prior art, it must also be mentioned that through the U.S. Pat. No. 5,347,520 it was previously made known that a BS-cell may be supplemented for activation connection (Enable Cell), and to connect a first test-controlling circuit 21 to the selecting element 14 while using several logical elements 24-28 in the form of NAND-gates.
What was shown and described in the U.S. Pat. Nos. 5,222,068; 5,042,034; 5,056,094 and 5,084,874 also belongs to prior art.
What was shown and described in the European patent publications 0,358,365; 0,358,371; 0,358,376; 0,514,700 and 0,589,223 also belongs to prior art.
The content of the U.S. Pat. No. 5,254,940 make known the requirements for creating, within an integrated circuit, the conditions for enabling, by means of multiplexers, a direct connection between the input nodes that belong to a selected integrated function block and the input pads that belong to the integrated circuit and a corresponding connection for the output nodes and pads.
The ability to test individual and selected function blocks through multiplexers is shown here. As shown, the connection of multiplexers gives access to the input and output nodes of internal function blocks through the input and output pads of the integrated circuit. However, because said multiplexers are a part of the functional signal path, they will cause an extra time-lag for the signals that appear at the functional signal path in question.
The publication does not indicate the use of test cells.
What was shown and described in the U.S. Pat. Nos. 5,331,571; 5,377,144; 5,195,050; 5,221,865; 5,230,000 and 5,225,834 also belongs to prior art.
With respect to the general tendencies within this technical field, it is clear that developments are such that the integrated circuit arrangements, which are available through producers and suppliers, are increasing in size (expected development of one million or more useable gate equivalents) with increasingly large and more complex function blocks and more complex coaction between the function blocks.
At the same time, testing systems and methods are growing in size and complexity, being accompanied by a rapid increase in the complexity and number of testing vectors that will be required.
Since the time for testing integrated circuits is valuable, and must therefore be kept short, great efforts are required to develop testing methods and testing vectors that can provide an accurate test of integrated circuits whose gate equivalents are growing in number.
Practical experience shows that the development of testing methods and vectors requires more time, where the increase in time is proportionally larger than the increase in the number of gate equivalents.